Today marks the introduction of a new product comprising of the N5X solutions into the eASIC family, whose official announcement surfaced at Intel FPGA technology day event. Mostly built to outdo the 5G wireless technology, this new product promises to provide up to 50% lower core power1 and lower unit-cost compared to the usual FPGAs.
With Intel comes the custom logic continuum of FPGAs, structured ASICs, and ASICs which produces technologies in faster and lower cost recurring in time to market (TTM), cost, power, volume, performance, and flexibility requirements.
It is considered to be the first structured eASIC solution with Intel FPGA compatible hard processor system. It helps reduce core power consumption and reduce recurring costs by 50%. Thus, it helps in creating better optimizations along with distinctiveness and smoother performance making the workflow easier.
Some of the features incorporated here are:
- Battery Performace, which helps in balancing low power and better battery performance
- Optimized TCO, which helps in reducing size for a given logic and I/O capacity
- The configured eCells helps in being configured as logic, arithmetic, or flip-flops, which further enables the optimizable platforms
- It has quad-core Arm® 64-bit hard processor subsystem (HPS) and secure device manager (SDM) 5 ported from Intel® Agilex™ FPGAs
Currently, it is made for providing the best time to market and helping launch high solutions at low cost.
