In a recent communication to investors, South Korea’s tech giant, Samsung, announced it will embark on mass production of its second-generation 3-nanometer (SF3) process and the performance-enhanced version of the 4-nanometer (SF4X) chips in the second half of 2024. The company unveiled its ambitious plans to utilize cutting-edge semiconductor manufacturing processes, marking a significant leap in its technological prowess.
Amidst the resurgence in mobile device demand and the ever-expanding high-performance computing (HPC) market, Samsung’s forthcoming chip production is expected to reverse previous setbacks and bolster the company’s growth. The second half of 2024 will witness the mass production of the second-generation 3nm and the fourth-generation 4nm HPC chips, designed to enhance Samsung’s competitive edge in the global semiconductor landscape.
Second-Generation 3nm (SF3): A Technological Marvel
Samsung’s second-generation 3nm (SF3) process is poised to be a significant upgrade from its first-generation 3nm counterpart (SF3E). While the current 3nm process primarily serves small mining chips, SF3 incorporates various enhancements, including gate-all-around (GAA) technology for transistor nanosheet channel width adjustments. This innovation significantly augments the functionality of these chips.
While Samsung refrains from direct comparisons between the two 3nm generations, the second generation undoubtedly exhibits superior performance. It boasts a 22% increase in execution performance under similar power and complexity, or a 34% reduction in power consumption with identical clock frequencies and transistor counts. Moreover, the chip area shrinks by 21%. These improvements are poised to revolutionize complex design choices and bolster the industry’s expectations for the upcoming SF3 chips.
Enhanced 4nm Version (SF4X) for HPC
Samsung is also introducing an enhanced version of its 4nm process, known as SF4X, designed specifically for high-performance CPUs and GPUs in data centers. This is the company’s first process tailored to meet the demanding needs of the high-performance computing (HPC) sector in recent years.
The enhanced 4nm version promises a 10% boost in performance and a 23% reduction in power consumption. While Samsung has not disclosed specific benchmarks, it is expected that these claims refer to the standard 4nm process flow. The enhancements encompass a redesign of transistor source and drain areas, rigorous evaluation of performance under high-stress conditions, and the integration of advanced transistor-level design technologies to maximize synergy.
Samsung’s aspirations include improving the MOL (middle-of-line) architecture and enabling the enhanced 4nm version to achieve a CPU silicon-verified minimum operating voltage (Vmin) of 60mV. This, in turn, reduces off-state current (IDDQ) variability by 10% and ensures stable high-voltage (Vdd) operation above 1V without compromising performance. Additionally, the enhanced version enhances SRAM (Static Random-Access Memory) control.
